1. Field of the Invention
The invention relates to a phase change memory, and in particular to a multilevel phase change memory.
2. Description of the Related Art
Phase change memories with competitive advantages of speed, low power consumption, high capacity, CMOS fabrication process compatibility and low costs, are suitable for use as high density stand-alone or embedded memories. Phase change memories are thus considered to have potentiality to replace currently commercial and competitive volatile memories such as SRAM and DRAM and non-volatile memories such as Flash. Bottlenecks in development of phase change memory mainly result from high writing current of the memory elements, since high writing current dictates increased area of connected driving transistors, leading to large memory cell area and low memory density. One method of increasing the phase change memory density is to decrease contact area between heater electrode and phase change recording layer so that the writing current can be reduced. However, this method is restricted by lithography and fabrication process technologies and thus harder to be implemented. Another method develops multilevel phase change memories with the same memory cells. However, this makes it difficult to control programming current and complicate process integration of various materials.
Multilevel phase change memories are proposed by Ovonyx in Elec_Memory_Research_Report in 1999, as shown in FIG. 1, by the relationship of memory state with writing current interval. Lateral axis represents writing current and vertical axis represents cell resistance resulting from the corresponding writing current. Different values of cell resistance are representative of different memory states. While an advantage of the multilevel operation can increase memory states, current programming intervals (1.42-1.51-1.51, 1.51-1.60, . . . , and 2.73-2.82 mA) corresponding to different memory states (or cell resistance) are extremely small and thus difficult to define and control, resulting in data storage errors. Additionally, resistance uniformity of respective states in different memory cells cannot be controlled precisely due to the possible deviation of fabrication process.
Japanese Matsushita Electronics Cooperation discloses another multilevel memory cell having various recording materials in U.S. Pat. No. 6,809,401. FIG. 2 is a cross section of a multilevel memory cell 200 disclosed therein. As shown, the multilevel phase change memory cell 200 comprises a substrate 21, a bottom electrode 22 and a top electrode 23, first to Nth recording layers 241-24N of different materials, and first to (N-1)th interlayers 251-25N-1 respectively disposed between two adjacent recording layers 241-24N. Although the multilevel phase change memory cell 200 provides multilevel operation, different properties of the recording layers 241-24N of different materials result in high control difficulty and fabrication process complexity.
Accordingly, a multilevel phase change memory cell having larger current programming intervals, recording layers of the same materials and simple fabrication process is called for.